Controlled impedance ensures that high-speed signals see a consistent transmission-line environment from driver to receiver. Trace impedance is governed by trace width and thickness, dielectric thickness and dielectric constant (Dk), and distance to the reference plane. When any of those vary, signals reflect, crosstalk grows, jitter increases and eye diagrams collapse.
Standard impedance targets
| Application | Target | Notes |
|---|---|---|
| General single-ended | 50 Ω | Most digital and RF interfaces |
| USB 2.0 / 3.x | 90 Ω diff | Differential pair, tight skew control |
| Ethernet, LVDS | 100 Ω diff | Reference planes critical |
| PCIe (Gen 3+) | 85 Ω diff | Loss-budget driven; low-loss laminate often required |
Tolerance classes
- Standard: ±10% — typical for non-critical designs
- Controlled: ±5% — most high-speed digital builds
- Tight: ±3% — RF, mmWave, very high-speed serial
What drives impedance
- Trace width and copper thickness (after etch compensation)
- Dielectric thickness above/below the trace
- Material Dk at the operating frequency (not just at 1 GHz)
- Solder mask presence and thickness on outer layers
- Copper foil roughness (especially at > 10 GHz)
Modeling and verification
Accurate impedance prediction requires field-solver calculations using the actual stackup, the laminate's published Dk at frequency, and precise dielectric thickness control. We coordinate with your designer on:
- Stackup definition and material selection
- Trace geometry adjustment (width / spacing / etch compensation)
- Reference-plane strategy and via transitions
- TDR test-coupon design and pre-shipment measurement
Engineering rule
For tighter than ±5% control, request a controlled-Dk laminate (e.g. Isola I-Tera MT40, Astra MT77, Megtron 6/7/8, Rogers RO4350B) and budget for TDR coupons on every panel.
Common impedance mistakes
- Routing high-speed signals over plane splits
- Treating Dk as constant across frequency
- Ignoring solder-mask effect on outer-layer microstrip
- Allowing reference-plane discontinuities at via transitions
- Inadequate copper-foil specification on long high-speed channels
Manufacturing controls at Sunrise
- Etch compensation tuned per material and copper weight
- Lamination pressure/temperature recipes per laminate family
- In-process dielectric thickness verification
- TDR measurement on customer-defined coupons
Applications
- DDR3/DDR4/DDR5 memory interfaces
- PCIe Gen3/Gen4/Gen5 backplanes and add-in cards
- 10G/25G/100G Ethernet and switch fabrics
- 5G base stations and antenna boards
- RF, microwave and mmWave assemblies
Need help on your build?
Talk to a Sunrise PCB engineer.