Rigid printed circuit boards are the structural and electrical backbone of high-performance electronic systems. Built from solid laminate substrates — FR-4, high-Tg epoxy, polyimide, metal core, or low-loss RF systems — they deliver mechanical stability, controlled impedance performance and long-term reliability in demanding environments.
Construction overview
A rigid PCB consists of laminated copper and dielectric layers bonded under heat and pressure.
- Copper foil (0.5 oz – 10 oz)
- Core laminate (FR-4, high-Tg, Rogers, polyimide, metal-core)
- Prepreg bonding layers
- Plated through holes (PTH)
- Blind & buried vias
- Microvias (laser-drilled, HDI)
- LPI solder mask
- Surface finish (ENIG, ENEPIG, HASL, OSP, immersion silver/tin, hard gold)
Materials & electrical properties
| Family | Tg | Dk | Df | Best for |
|---|---|---|---|---|
| Standard FR-4 | 130 – 140 °C | ≈ 4.2 – 4.6 | 0.015 – 0.025 | General-purpose digital and analog |
| High-Tg FR-4 | 170 – 180 °C | ≈ 4.0 – 4.5 | 0.012 – 0.020 | Lead-free assembly, automotive, industrial |
| Low-loss / RF (Rogers, PTFE) | ≥ 280 °C | 2.2 – 3.7 | < 0.005 | RF, microwave, ≥ 10 Gbps digital |
| Metal core (Al / Cu) | — | — | — | LED, power electronics, dense thermal management |
Multilayer stackup engineering
Signal integrity and EMI control depend heavily on proper stackup design.
- Symmetric stackups to prevent warpage
- Dedicated ground reference planes adjacent to high-speed signals
- Controlled dielectric thicknesses for impedance targets
- Balanced copper distribution per layer
- Sequential lamination for HDI architectures
Example: 6-layer high-speed stackup
- L1 – Signal (controlled impedance)
- L2 – Ground
- L3 – Signal
- L4 – Power
- L5 – Ground
- L6 – Signal
Controlled impedance & signal integrity
We support impedance-controlled routing for microstrip, stripline, and edge- or broadside-coupled differential pairs.
| Parameter | Standard | Tighter option |
|---|---|---|
| Impedance tolerance | ± 10% | ± 5% (or ± 3% by request) |
| Verification | Coupon-based | TDR with full report |
| Variables controlled | Dielectric thickness, trace width, copper thickness | + etch compensation, resin content, glass style |
Via technologies
| Via type | Capability | Typical use |
|---|---|---|
| Plated through hole (PTH) | Aspect ratio up to 10:1 | Standard interconnect |
| Blind & buried | Sequential lamination | Routing density, BGA breakout |
| Microvia (HDI) | Laser-drilled, ≈ 75 – 150 µm | Fine-pitch BGA, HDI stacks |
| Via-in-pad (VIPPO) | Filled & planarized | Reduces parasitic inductance |
Copper weights & current capacity
- 0.5 oz (17 µm) — fine-line HDI outer layers
- 1 oz (35 µm) — standard digital / signal
- 2 oz (70 µm) — power planes, moderate current
- Heavy copper up to 10 oz — power distribution, motor drives, industrial supplies
Fabrication capabilities (typical ranges)
| Parameter | Range |
|---|---|
| Layer count | 1 – 20+ |
| Board thickness | 0.4 mm – 3.2 mm |
| Min trace / space | 3 / 3 mil (HDI) |
| Min mechanical drill | 0.15 mm |
| Microvia size | ≈ 0.075 mm |
| Aspect ratio | Up to 10:1 |
Standards & reliability
- IPC-A-600, IPC-6012, IPC-2221 / 2222
- IPC Class 2 and Class 3
- RoHS compliance
- UL certification
- Optional: microsection, solderability, thermal stress and ionic contamination testing
Design guidelines that always pay off
Maintain consistent reference planes, keep aspect ratios reasonable, balance copper across the stack, follow minimum annular ring rules, and lock down the impedance stackup before layout finalization. Bring us in early — pre-production DFM review on the actual Gerbers prevents most of the rework we see.
Need help on your build?
Talk to a Sunrise PCB engineer.