PCB stackups — engineering the foundation of signal integrity.

A PCB stackup is the vertical arrangement of signal layers, power planes, ground planes, dielectric cores and prepreg bonding layers. These are laminated under heat and pressure into a rigid multilayer structure. Stackup decisions directly drive signal integrity, controlled impedance, EMI/EMC performance, power distribution, thermal behavior, mechanical reliability and manufacturability.

Why stackup design matters

1. Signal integrity (SI)

Trace impedance is governed by trace width, copper thickness, dielectric thickness, dielectric constant (Dk) and distance to the reference plane. Poor stackups cause impedance mismatch, reflections, crosstalk, jitter and eye-diagram degradation.

2. Power integrity (PI)

A well-designed stackup gives low-inductance power distribution, tight power-ground coupling, reduced ripple and stable decoupling. Place power adjacent to ground to minimize loop inductance.

3. EMI / EMC control

Continuous reference planes reduce radiated emissions, shrink loop areas, preserve return-current continuity and shield high-speed signals. Striplines (between planes) are especially effective.

4. Mechanical stability

Symmetrical stackups and copper balancing prevent warpage, bow/twist, delamination and uneven copper stress.

Common stackup configurations

Core components of a stackup

• Signal layers — microstrip on outer layers, stripline embedded between planes for better EMI containment and stable impedance.
• Ground planes — provide stable reference, return paths, noise reduction and EMI shielding. Continuity is critical at high speed.
• Power planes — deliver stable voltage; place adjacent to ground for low-inductance coupling.
• Core material — rigid laminate (FR-4 or high-performance) with copper bonded both sides; provides structural strength.
• Prepreg — fiberglass impregnated with resin; bonds layers and controls dielectric thickness during lamination.

Materials used in stackups

Controlled impedance in stackups

Common targets include 50 Ω single-ended, 90 Ω differential (USB), 100 Ω differential (Ethernet, LVDS) and 85 Ω differential (PCIe). Accurate modeling requires field-solver calculations, known Dk at the operating frequency, and precise dielectric thickness control.

• Standard tolerance: ±10%
• Controlled: ±5%
• Tight control: ±3%

Symmetry and copper balancing

A well-designed stackup is symmetrical around its centerline. Copper balancing prevents uneven thermal expansion, warping and lamination stress.

HDI stackups

HDI designs use blind vias, buried vias, microvias and sequential lamination to enable fine-pitch BGA breakout, higher routing density and reduced board size. They demand advanced fabrication control.

Manufacturing considerations

• Lamination pressure and temperature must be tightly controlled.
• Dielectric thickness must remain consistent across the panel.
• Etch compensation adjusts trace widths to hit impedance targets.
• Registration alignment ensures accurate layer-to-layer position.

Conclusion

PCB stackup design is the electrical and mechanical foundation of any multilayer board. As data rates rise and densities increase, stackup planning is no longer optional — it is essential for predictable performance. Engaging Sunrise PCB early ensures impedance targets, materials and tolerances align with your design goals.